The present invention relates to a semiconductor integrated circuit device and, more particularly, to techniques effective when applied to a semiconductor integrated circuit device having a SRAM (Static Random Access Memory).
The SRAM has a memory cell arranged at the intersections between complementary data lines and a word line. The memory cell is composed of a flip-flop circuit and two transfer MISFETs having their individual semiconductor regions connected with the paired input/output terminals of the flip-flop circuit.
The flip-flop circuit is used as an information storage unit and has its input/terminal portions acting as information storage nodes. The flip-flop circuit is composed of two driver MISFETs and two high resistance load elements. These high resistance load elements are made of a polycrystalline silicon film which is doped with none or a slight amount of impurity for reducing the resistance. The high resistance load elements are arranged over the gate electrodes of the driver MISFETs. These high resistance load elements are featured by reducing the area of the memory cell to highly integrate the SRAM because they are arranged over the driver MISFETs.
The transfer MISFETs have their one-side semiconductor regions connected with the gate electrodes of the driver MISFETs. These connections are effected by forming connection holes in an insulation film over the one-side semiconductor regions of the transfer MISFETs and by extending the one-end sides of the gate electrodes of the driver MISFETs through the connection holes to connect them directly with the one-side semiconductor regions of the transfer MISFETs.
The gate electrodes of the transfer MISFETs of the memory cell are connected with a word line. The other semiconductor regions of the transfer MISFETs are connected with complementary data lines. These complementary data lines are constructed to extend over the high-resistance load elements. A power source voltage line and a reference voltage line are connected through the high resistance load elements and the driver MISFETs, respectively, with the information storage nodes of the flip-flop circuit of the memory cell.
The memory cell of this kind has a tendency to have its size reduced the more, as the high integration advances, thereby to drop the charge storages of the information storage nodes. This drop of the charge storages is liable to destroy the information storage nodes (so called softerror) due to the incidence of alpha rays.
The most proper technique for solving this problem is disclosed in U.S. Pat. No. 4,590,508. According to this technique, capacitance elements are connected with the information storage nodes of the memory cell of the SRAM to increase the charge storages of the information storage nodes. These capacitance elements are constructed by incorporating a dielectric film while using the gate electrodes of the driver MISFETs as one electrode and by laminating a polycrytalline silicon film as the other electrode.
Incidentally, the SRAM is disclosed on pp. 71 to 87 of "Nikkei Micro-Device" published in August, 1987 by Nikkei McGrow-Hill, for example.